10.5 Broadband ESD Protection Circuits in CMOS Technology

As device dimensions scale down and the operating speed of integrated circuits scales up, electrostatic discharge (ESD) proves an increasingly more critical issue. With hundreds of gigahertz I/O pads in typical data communication circuits, microprocessors, and memories, both the voltage tolerance and the area of ESD protection devices become important design parameters. It is possible to use inductive peaking to improve the bandwidth, but, with an ESD capacitance of 1.2pF, the impedance mismatch at the input or output results in S11 or S22 of only -4dB at 5GHz, corrupting broadband data considerably. Also, distributed ESD structures [1] suffer from the loss-capacitance trade-off of onchip transmission lines and require a large area. For example, a metal6-metal1 microstrip designed to absorb an ESD capacitance of 1.2pF must be 8mm long and 14μm wide while introducing 1.5dB of midband loss. The distribution of the ESD capacitance over a resistive line may also compromise the voltage tolerance because an ESD event injects a large current into the line, creating a potential gradient from one end to the other.